Xilinx reVISION sample test 1 (file_IO)

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本文記錄如何使用Xilinx ZC702 執行reVISION 範例程式。


Step1: 安裝及下載
  • Install SDx 2017.2 (2018.2不支援ZC702) 
  • Download ZC702 reVISION package (reVISION package) 
Step2: 設定環境變數後，執行SDx 2017.2 (參考: FPGAの部屋)
  • source /opt/Xilinx/SDx/2017.2/settings64.sh 
  • export SYSROOT=～/zc702_trd/sw/sysroot/ 
  • sdx 
Step3: 於SDx開啟reVISION範例程式(ex:bilateral-File I/O)並編譯
  • New project => Xilinx SDx project => Add Custom Platform (zc702_trd) => bilateral-File I/O => Active build configuration (release) => Build
Step4: 測試
  • 複製所有於Release/sd_card路徑下的檔案至SD卡 
  • 將SD卡插入ZC702, power on 
  • 使用GtkTerm tool 連接Host端與ZC702 (設定port number, baud rates,..) 
  • cd /media/card 
  • 執行.elf檔 
Reference:
Note(1): It's necessary to change network name to "eth0" for SDx license manager

Reference: 
https://askubuntu.com/questions/767786/changing-network-interfaces-name-ubuntu-16-04

Note(2): Add parameter "zc702_trd" in "board" option of description.json file to enable use of stereo sample. 

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